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Recent Publications

FuncAnoDe: A Function Level Anomaly Detection in Device Simulation

Authors : Taeil Oh, Hong Chul Nam, Chanwoo Park, Hyunbo Cho

Publication : SISPAD

Date : September 2024

In semiconductor device simulations, the reliance on empirical compact models, such as the Berkeley Short-channel IGFET Model (BSIM) and neural compact models, introduces approximations that may significantly diverge from actual physical phenomena. Identifying and filtering out unphysical behaviors and erroneous simulation outcomes is a challenging task, traditionally requiring extensive expert involvement and incurring high costs. In response, we introduce FuncAnoDe, a novel neural operator for unsupervised functional anomaly detection in semiconductor simulation datasets. FuncAnoDe is the first to offer deep learning-based function-level anomaly detection without manual expert intervention. Its function-level encoder-decoder architecture enables applications across a diverse range of device parameters and simulations, ensuring scalability and high accuracy in identifying physically implausible parameter configurations. Our evaluations were conducted through complex capacitance-voltage (C-V) curve analysis, and FuncAnoDe demonstrated its effectiveness in anomaly detection by achieving a 100.00% accuracy without reliance on manual labeling. FuncAnoDe provides a methodological advancement that enhances the precision, reliability, and efficiency of semiconductor design and simulation workflows.

Enhancing Interpretability of Neural Compact Models: Toward Reliable Device Modeling

Authors : Chanwoo Park, Hyunbo Cho, Jungwoo Lee

Publication : IEEE Journal of the Electron Devices Society (JEDES)

Date : June 2024

Neural Compact Models (NCMs) have emerged as a crucial tool to meet the stringent demands of Design-Technology Co-Optimization (DTCO) and to overcome the complexities and prolonged development cycles encountered in traditional compact model creation. Despite their efficiency in simulating electronic devices, a significant barrier to the widespread adoption of NCMs in the industry remains: the lack of interpretability. In the semiconductor sector, where inaccuracies or failures can lead to considerable financial consequences, it is critical to ensure that the model’s predictions are both understandable and reliable. This study aims to enhance the interpretability of NCMs used for I-V and C-V characterizations by clarifying the physical significance of latent vectors. A regularization technique is employed to disentangle features within the latent space, and interpolation is used to visualize and elucidate each dimension’s physical impact. Our approach, which offers interpretable insights into the model’s functionality, seeks to encourage broader implementation of NCMs in the industry, thus accelerating advancements in DTCO.

2024

FuncAnoDe: A Function Level Anomaly Detection in Device Simulation

Taeil Oh, Hong Chul Nam, Chanwoo Park, Hyunbo Cho | SISPAD | September 2024

Enhancing Interpretability of Neural Compact Models: Toward Reliable Device Modeling

Chanwoo Park, Hyunbo Cho, Jungwoo Lee | IEEE Journal of the Electron Devices Society (JEDES) | June 2024

Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation

Chanwoo Park, Seungjun Lee, Junghwan Park, Kyungjin Rim, Jihun Park, Seonggook Cho | IEEE Journal of the Electron Devices Society (JEDES) | June 2024

Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device Modeling

Chanwoo Park*, Junghwan Park*, Premkumar Vincent, Hyunbo Cho (*Equal contribution) | ACM/IEEE Design Automation Conference (DAC) | June 2024

Inducing Point Operator Transformer: A Flexible and Scalable Architecture for Solving PDEs

Seungjun Lee, Taeil Oh | Proceedings of the AAAI Conference on Artificial Intelligence | February 2024
2023

NPC-NIS: Navigating Semiconductor Process Corners with Neural Importance Sampling

Hong Chul Nam, Chanwoo Park | NeurIPS 2023 Workshop on Adaptive Experimental Design and Active Learning in the Real World | December 2023

DAT: Leveraging Device-Specific Noise for Efficient and Robust AI Training in ReRAM-based Systems

Chanwoo Park, Jongwook Jeon, Hyunbo Cho | SISPAD | September 2023

FlowSim: An Invertible Generative Network for Efficient Statistical Analysis under Process Variations

Chanwoo Park*, Hong Chul Nam*, Jihun Park, Jongwook Jeon (*Equal contribution) | SISPAD | September 2023

Performance Evaluation of Strain Effectiveness of Sub-5 nm GAA FETs with Compact Modeling based on Neural Networks

Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh | IEEE EDTM | March 2023

Neural Compact Modeling: Motivation, State of the Art, Future Perspectives

Hyunbo Cho | IEEE EDTM | March 2023

Hierarchical Mixture-of-Experts approach for neural compact modeling of MOSFETs

Chanwoo Park, Premkumar Vincent, Soogine Chong, Junghwan Park, Ye Sle Cha, Hyunbo Cho | Solid-State Electronics Volume 199, 108500 | January 2023
2022

A novel methodology for neural compact modeling based on knowledge transfer

Ye Sle Cha, Junghwan Park, Chanwoo Park, Soogine Chong, Chul-Heung Kim, Chang-Sub Lee, Intae Jeong, Hyunbo Cho | Solid-State Electronics Volume 198, 108450 | December 2022
2021

Knowledge-based neural compact modeling towards autonomous technology development

Soogine Chong | MOS-AK | August 2021

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