Unified Dynamic Library: Neural Network-Based Compact Modeling for Enhanced Efficiency

Authors: Hyunseok Whang, Donghyun Jin, Wanki Lee, Kyungjin Rim, Changsub Lee, Ye sle Cha

Publication: International Compact Modeling Conference (ICMC)

Date: June 2025

This study introduces the new concept of Unified Dynamic Library(UDL) to overcome existing limitations and proposes a novel method for ANN-based compact modeling. Using this method, it becomes possible to adopt the computational framework of neural networks, achieving high simulation speeds. In addition, it offers the advantage of incorporating the physical phenomenon of components into the device modeling process, such as negative differential resistance. To validate this concept, our model's accuracy and simulation speed have been compared with the direct implementation of ANN model in Verilog-A as well as the Look-Up Table model. In the transient Ring Oscillator circuit simulations, the UDL calculation achieved a speed 43 times faster than the Verilog-A-based neural network model and 389 times faster than the Look-Up Table model while sufficiently guaranteeing model accuracy.

Large Pre-Trained Model Approach for Efficient Design Technology CO-Optimization

Authors: Premkumar Vincent, Yeongwoo Nam, Kyungmin Kim, Hong Chul Nam, Johyeon Kim, Hyunseok Whang

Publication: International Compact Modeling Conference (ICMC)

Date: June 2025

In this work, we present a novel approach using large pretrained models to generate compact models for semiconductor devices, accelerating design technology co-optimization (DTCO) in advanced technology nodes. Our pretrained models, initially trained on SPICE-generated planar MOSFET datasets, demonstrate strong adaptability to state-of-the-art logic technologies while maintaining high accuracy. By integrating these models with device-specific artificial neural networks (ANNs), we enable rapid compact model generation even with limited data. We validate our approach through DTCO analysis of vertically stacked nanosheet-based GAA-FETs, showing that it requires significantly fewer data points compared to conventional methods while enhancing both accuracy and simulation speed.